Ŀ´Ƽ
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Ŀ´Ƽ õԽù
| õ | ֱٴ۴ | ()
Ŀ´Ƽ õԽù
| õ | ֱٴ۴ | ()
Ŀ´Ƽ õԽù
| õ | ֱٴ۴ | ()
Ŀ´Ƽ õԽù
| õ | ֱٴ۴ | ()
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̿ ɼǵ |
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̿ 캸ڽϴ. DFI Ǵн/ ̿ äϴ¸ŭ DK P45 T2RS+ Դϴ. ̹ 信 Ŭ Genie BIOS Setting 캾ϴ.
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Genie BIOS Setting 캸 ִ ɼ ϳ. PC Health Status ϵ ѵ, Adjust CPU Temp, CPUµ Ƿ +/- ִ. PWMǴ CPU RPM Ƿ ǵ帱 ־ մϴٸ, κ ϴٴ ǥ ʷ ְ. κ忡 ִ Ʈ , µ ʽϴ.
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, DFI κ ! Genie BIOS SettingԴϴ. ϴ ̰ δ ƴ 켱 ⺻带 ϰڽϴ.
- CPU Feature : CPU õ .
- DRAM Timing : Ÿ̹ . Ŭ (Ŭ Ͻ ) Ĩϴٸ ΰ ʿ κ̱ .
- Voltage Setting : CPU/NB/VTT/PLL а .
- AC Shutdown free :
- O.C Fail retry Counter : Ŭ н ڵ õ Ƚ. Ƚŭ ÿ ϸ µ˴ϴ.
- O.C Fail CMOS Reload : Ŭ н ٽ ҷ CMOS ð մϴ. CMOS Reloaded ũ1 4 ϴ ũȣ Ͽ ش ҷ ˴ϴ.
- CPU Clock Ratio : CPU . CPU Ŭ ý۹ Ŭ ̷ϴٸ Ϲ μ Ǿ ְų θ ϴٴ ϼ. (ͽƮ )
- CPU N/2 Ratio : Disable , Enable 0.5 (ex. 7.5, 8.5 )
- Target CPU Clock : CPU Ŭ.
- CPU Clock : ⺻ Ŭ . κ Ͽ Ŭϰ ˴ϴ. 500 x 7 = 3500MHz Ǿ ֽϴ.
- DRAM Speed : CPU-RAM Ŭ к Ÿϴ. 200/400, 200/667, 266/667, 266/800, 333/667, 333/800, 333/1066, 400/800 Ʈ(̴) մϴ. 밳 266/667(4:5), 266/800(2:3), 333/667(1:1), 333/800(5:6) ð ַ մϴ.
- Target DRAM Speed : CPU Clock ð DRAM Speed ð ŬԴϴ.
- PCI-E Clock : PCI Express ñ׳ ļ Դϴ. 100MHz +/- 1~2MHz ϴٸ Ŭ ñ׳ ߳ ġ δ Ƿ ǵ帮 ʴ .
- CPU Spread Spectrum / PCIE Spread Spectrum : ̰ ڱ̳ ǻͰ Ͻ е ͼϽ . PC ġ û پ Ŭļ ̷ ñ׳ ְޱ ̷ ñ׳ ļ EMI(Electro Magenetic Interference), ڱⰣ ̱ ñ׳ źȭŰ Spread Spectrum̶ մϴ. ̰ Enable Ű SCSI EMI ΰ Ŭ ɷ Ǵ .
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ؼ CPU Features.
- Theraml Management Control - ״ CPU Դϴ. Thermal Throttle̶ . ⺻ ״ ϴ.
- PPM(EIST) Mode - Enhanced Intel Speedstep Technology Դϴ. CPU Ͽ ̵ ʿ Ŭ Ͽ Һ ̴ ȿ ϴ.
- Limit CPUID MaxVal - Ȯ CPU ID ν Ұ 9x̳ NT ü ˴ϴ. 2K, XP, Ÿ ״ Disable ѳø ˴ϴ.
- C1E Function : C1 state Enhancement ڷ EIST Բ Һ ϳԴϴ. ̵ CPU ߰ CPU ʴ off Һ ص . Ŭ ÿ DZ , AMD CnQ(Cool And Quite) ξ پ ֽϴ.
- Execute Disable Bit : ̷ . Ǽ ڵ峪 ̷ ǿ ִ Ư ˰ մϴ.
- Virtualization Technology : ȭ . Ƽ OS ӽ ȰǴ Դϴ. ӽſ CPU ڿ ϵó Ҵ ִٴ . ڵ Ǯ Ҹ մϴ.
- Core Multi-Processing : ״ Ƽھ Ȱȭ ϰڳĴ ǹԴϴ. Disableϸ ̱ھ ۽ų ֽϴ.
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DRAM Timing
- CAS Latency, RAS to CAS Latency, RAS Precharge, Precharge Delay Ϲ ϴ Դϴ. 800MHz 5-5-5-15 ϸ 1000MHz 5-5-5-15 ϴ . 翬 Ŭ , Ÿ̹ Ͻô ϴ.
Ŭ 1000MHz 4-4-4-12 ϴ ǰ . :)
- REF to ACT Delay tRFCε Ǵµ ? to Active, IC Row/Col ٽ Ȱ· ٲ Ͻø մϴ. ̰ IC縶 ġ ٸ, 븸 PSC(ĿĨ)迭 IC ϴ ټ 800MHz 42~50, 1000MHz 55~60 ̰ Ŭ ̴н BP8̳ ũ D9Gxx迭 IC 1000Mhz ̻ 30 մϴ. 翡 Ƿ Ѱġ ãƳų, Ȥ Auto νô ϴ. ϴٸ, 36 ̻ ɻ ̰ ġ ټ Ŭ öϴ.
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Voltage SettingԴϴ.
- CPU VID Special Add : ⺻ ߰ ΰ ΰ ϴ Դϴ. 12.5mV(0.0125V). CPU Vid Ǵµ, ̰ C1E/EIST Ǿ ̵/Ǯε а Դϴ. CPU Vid ݾ ٸϴ. CPU Vid⺻ 1.15V, Vid Max 1.25V̴.
ִ CPU VID Special Add CPU ü Vid Max Vid ⺻ + Vid Special Add Vid Max ˴ϴ. E8400 3.5GHz Ŭ ϴµ Vid Max 1.15V + 37.5mV = 1.19V ȭ ϴ. , ⺻ 1.25V ΰ ְ ˴ϴ.
- DRAM Voltage Contol : ? ణ ֱ 0.01V شٴ ΰ ϼž մϴ. Ƽ Ÿ 庸 Ŭ մϴ.
- SB Core / CPU PLL Voltage : PLL Phase Look Lock ڷ Ŭ ʷ ǹϴ°ɷ Դϴ. 콺긴 ھ б Ǵ±. 1.55V ⺻̰ Ŭ 1.75V ΰϴ 쵵 ϴ.
- NB Core Voltage : 뽺긴 . ھ2 CPU Ŭ Ŭ ʿ MCH(Memory Control Hub) 뽺긴 ΰؾ մϴ. ⺻ 1.18V Ŭ DK P45 1.3V ʿմϴ. ٸ ̴ а , ֽϴ.
- CPU VTT Voltage : FSB ñ׳ . Ŭ ö VTT е ÷ մϴ. DK P45 뽺긴 а ø õմϴ.
- Clockgen Voltage Control : Ŭ ʷ . ⺻ ʿ ϴٸ Ȥ CPU FSB 600 ̻ ø ÷ָ 찡 ֱ մϴ. Case by case̹Ƿ ũ κ ƴմϴ.
- CPU GTL 0/2, 1/3 REF Voltage : GTL ȣ° ֽϴ. GTL μ Ĩ ̵ ñ׳ ſ ŰĶ ִµ, GTL VTT(Ȥ FSB)п ȣ ĺΰ ϴ. Ư Ŭ GTL REF, GTL ȣ ĺ е ö ϴµ ٷ а ϴ Դϴ. Ϲ VTTд 0.67(67%)~0.58(58%) մϴٸ ̹ϰ Ŭ ¿ϴ ã 밡ٰ ʿ κԴϴ.
- North Bridge GTL REF Voltage : CPU GTL REF , ̰ 뽺긴 ñ׳ ĺ GTL Դϴ. 뽺긴 ö ۼƼ մϴ. ã⸦ 밡ٴ ʼ.
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CMOS Reloaded Ϸ ٽ ҷ ִ Դϴ. ABS(Auto Boost System) , CMOS Reloaded ̿ ҷ̴ ƩɼԴϴ. ȿ ۵ϴ Ŀ̶ ϴ.
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ݱ ⺻, ʹ ɼ! |
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ݱ 캻 ɼ ͼġ ȭ Դϴ. ̿ ʱȭ鿡 F9Ű (Advanced) ֽϴ. Advanced Ͽ ٽ 캼?
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Genie BIOS Setting û þ Ȯ ֽϴ. ̵带 ۼϰ ִ ɼǵ ¹Դϴ. ˾Ƶξ κ Ȯ .
- Boot Up Clock : ⺻ FSB մϴ. Auto մϴ.
- CPU Clock Amplitude : CPU Ŭ ñ׳ ϴ κεմϴ. Ϲ ⺻ ״ մϴ. ʿ 100mV ÷ .
- CPU Clock0/1 Skew :Skew ȸο Ŭļ ð ǹմϴ. Ƹ Ŭ ñ׳ ð κ ϴ . Clock0, Clock1 ǹϴ ٴ ϴٸ, · Ŭ CPU Ŭ ñ׳ ȭ ǿ ʿ κ̶ ˴ϴ. pico seconds. (10 1)
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DRAM Timing κе û ɼ ߰Ǿϴ. Ͻ κ ռ ߱ ũ 캼 κ ߰ Ÿ̹ 鵵 Auto Ƶ ϴ. ٸ ܿ ߰ ɼǵ ߰.
- Enhance Data transmitting : ۼ ø ִ Դϴ. Ϲ Auto FAST, Turboε ֽϴ. Turbo ϰ Ŭ ƴ ʴ ϴ. FAST մϴ.
- Enhance Addressing : ˴ϴ. Auto, Normal, Fast ȭ Ǿ ְ 2ns Ͻ ȿ ֽϴ.
- T2 Dispatch : κе , 뽺긴 MCH ū ϰ ɸϴ. 䱸ϴ е ü Ŭ پ ɼ ֽϴ. ⺻ Auto Ŭ Disable ϴ õմϴ. ø ʹٸ Auto ߰ؾ մϴ.
- Clock Setting Fine Delay : äκ Ͻ ð ִ Դϴ.
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- CH1/CH2 DRAM Default Skew : FSB Ŭ ʿ κԴϴ. 귣忡 ð ɵ ̰ ֽϴ. ġ ŸƮϰ ɵ ŭ Ŭ ȵ˴ϴ. ⺻ 0 3~5 Ŭ ټ ȭ ִ°ɷ Դϴٸ, IC Ư ϰ ٸǷ 밡ٰ ʿ κԴϴ.0 7 8 ѵ, 0ܰ谡 鼭 Ͻð ڰ Ͻð Ǯϴ. ġ ٽ ̿ Ͽ Clock Fine Delay Ȯ Ȯ ̰ .
- RCOMP Setting : Ŭ ȭ ġ մϴ. DFI Ͼ 1 2 ̿ ϴ° ٰ ϴ.
- CH1/2 Clock Crossing Setting, CommonClock Setting 鵵 Ͻ ȿ ִ Դϴ. Aggressive, More Aggressive ش μ ѹ ְ ̰ ϳ ϳ ֽϴ. CPU/ Ŭ ȭ ϷǾٸ, ̰ ͵ . ̰ ġ Ͽ ϵǹǷ ġ ã ߿մϴ.
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ÿɼǵ. ü ̹ տ Ƿ ߰ ʿ ̴ϴ.
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м մϴ. DFI Ƽ ٿ ?
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7
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ȣ ٸ
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̶ õּ. α ʾƵ õ Ͻ ֽϴ. |
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Խù |
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õȳ |
Խù õ ֽϴ.õ 5 ̸̻ ο Խù ɾ 帳ϴ.
Ʈ ̺Ʈ Ͻþ ǰ ư ֽϴ.
Ʈȳ ۼ : 20, õŬ : 2, õ 2, ۼ : 4 (2008.12.29Ϻ) |
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